Step 1: Analyzing the Design File

Step 1: Analyzing the Design File - 2020.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2020-11-23

Version

2020.2 English

To begin, analyze your HDL source files by type, as shown in the table below. Each command can take multiple files.

Table 1. File Types and Associated Commands for Design File Analysis
File Type	Command
Verilog	`xvlog <VerilogFileName(s)>`
SystemVerilog	`xvlog -sv <SystemVerlilogFileName(s)>`
VHDL	`xvhdl <VhdlFileName(s)>`