Using Mixed Language Simulation - 2020.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2020-11-23
Version
2020.2 English

The Vivado simulator supports mixed language project files and mixed language simulation. This lets you include Verilog/SystemVerilog (SV) modules in a VHDL design, and vice versa.