VHDL and Verilog Values Mapping - 2020.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2020-11-23
Version
2020.2 English

The following table lists the Verilog states mappings to std_logic and bit.

Table 1. Verilog States mapped to std_logic and bit
Verilog std_logic bit
Z Z 0
0 0 0
1 1 1
X X 0
Note: Verilog strength is ignored. There is no corresponding mapping to strength in VHDL.

The following table lists the VHDL type bit mapping to Verilog states.

Table 2. VHDL bit Mapping to Verilog States
bit Verilog
0 0
1 1

The folowing table lists the VHDL type std_logic mappings to Verilog states.

Table 3. VHDL std_logic mapping to Verilog States
std_logic Verilog
U X
X X
0 0
1 1
Z Z
W X
L 0
H 1
- X

Because Verilog is case sensitive, named associations and the local port names that you use in the component declaration must match the case of the corresponding Verilog port names.