SDC and XDC Constraint Support - 2020.2 English

The Vivado Design Suite implementation is a timing-driven flow. It supports industry standard Synopsys Design Constraints (SDC) commands to specify design requirements and restrictions, as well as additional commands in the Xilinx Design Constraints format (XDC).

Figure 1. Vivado Design Suite High-Level Design Flow

Vivado Implementation Sub-Processes

The Vivado Design Suite implementation process transforms a logical netlist and constraints into a placed and routed design, ready for bitstream generation. The implementation process walks through the following sub-processes:

1. Opt Design: Optimizes the logical design to make it easier to fit onto the target Xilinx device.
2. Power Opt Design (optional): Optimizes design elements to reduce the power demands of the target Xilinx device.
3. Place Design: Places the design onto the target Xilinx device and performs fanout replication to improve timing.
4. Post-Place Power Opt Design (optional): Additional optimization to reduce power after placement.
5. Post-Place Phys Opt Design (optional): Optimizes logic and placement using estimated timing based on placement. Includes replication of high fanout drivers.
6. Route Design: Routes the design onto the target Xilinx device.
7. Post-Route Phys Opt Design (optional): Optimizes logic, placement, and routing using actual routed delays.
8. Write Bitstream: Generates a bitstream for Xilinx device configuration. Typically, bitstream generation follows implementation.

For more information about writing the bitstream, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).