QoR Assessment Details - 2020.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2021-01-25
Version
2020.2 English

The QoR Assessment Details table (shown in the following figure) gives a convenient design overview that highlights issues in the following areas:

  • Utilization
  • Clocking
  • Congestion
  • Timing

These categories form the basis of the RQA score. The following figure shows an example report.

Figure 1. QoR Assessment Details

The table shows design characteristics broken into 4 categories. Each category is marked OK when there are no sub-items marked REVIEW. When sub-items are marked REVIEW, the failing item is displayed with its threshold and current value. The thresholds are not hard limits and can be exceeded, but going over these limits can make timing closure difficult. Pay particular attention when thresholds are significantly exceeded or when many categories are exceeding their thresholds.

Utilization checks are performed on the whole device, at the SLR level and the pblock level. Running report_qor_suggestions can help reduce utilization.

Clocking shows whether there is high clock skew on setup or hold paths. Running report_qor_suggestions gives more information on the paths that are impacted by sub optimal clocking and in some cases automated fixes.

Congestion looks into the netlist for profiles that can contribute to routing congestion. Congested region information is not available before placement but some netlist items are available. You may wish to evaluate congestion by running place and route before fixing these items. They do not contribute to the RQA score before the design is placed. Run report_qor_suggestions to generate suggestions that reduce congestion targeted at cells in the congested area.

Timing looks at the current estimated timing and also performs net and LUT budget checks. LUT and net budget checks provide an alternate view of a timing path. Most component delays are fixed, but LUT delays can change during implementation. Net delays can also vary. These checks replace the net and LUT delays with some typical numbers as opposed to more optimal numbers. This can help account for when the tool has to compromise by optimizing a more critical path at the expense of another. It is recommended to fix these paths early as they will be challenging to meet timing. Run report_qor_suggestions to get more information on these paths.