Report Timing Summary - 2020.2 English

Timing analysis is available anywhere in the flow after synthesis. You can review the Timing Summary report files automatically created by the Synthesis and Implementation runs.

If your synthesized or implemented design is loaded in memory, you can also generate an interactive Timing Summary report from:

• Flow Navigator > Synthesis
• Flow Navigator > Implementation
• Reports > Timing > Report Timing Summary

Equivalent Tcl command: report_timing_summary

For more information on the report_timing_summary options, see this link in the Vivado Design Suite Tcl Command Reference Guide (UG835).

In a synthesized design, the Vivado® IDE timing engine estimates the net delays based on connectivity and fanout. The accuracy of the delays is greater for nets between cells that are already placed by the user. There can be larger clock skew on paths where some of the cells have been pre-placed, such as I/Os and GTs.

In an Implemented Design, the net delays are based on the actual routing information. You must use the Timing Summary report for timing signoff if the design is completely routed. To verify that the design is completely routed, view the Route Status report.

When run from the Tcl Console or the GUI, the report can be scoped to one or more hierarchical cells using the -cells option. When the report is scoped, only paths with the datapath section that start, end, cross, or are fully contained inside the cell(s) are reported.