Summary by Clock Pair - 2020.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2021-01-25
Version
2020.2 English

In the Summary (by clock pair) section, useful information about the number of CDC paths between two clocks are presented, along with the severity of the most critical issue found among these paths. The table includes the following columns:

  • Severity: Reports the worst severity of all CDC paths from/to the listed clocks. Values are Info, Warning, or Critical.
  • Source Clock: Shows the name of the CDC Source Clock.
  • Destination Clock: Shows the name of the CDC Destination Clock.
  • CDC Type: Reflects the relationship between two clocks and their dominant timing exception, if any. Possible types are:
    • Safely Timed: All CDC paths are safely timed because the clocks are synchronous and accurate timing is not prevented by a timing exception.
    • User Ignored: All CDC paths are covered by set_false_path or set_clock_groups.
    • No Common Primary Clock: The CDC clocks are asynchronous and at least 1 CDC path is normally timed between two clocks that do not have a common primary clock.
    • No Common Period: The CDC clocks are asynchronous and at least 1 CDC path is normally timed between two clocks that do not have a common period. For the definition of clocks with no common period, refer to Understanding the Basics of Timing Analysis.
    • No Common Phase: The CDC clocks are asynchronous since there is no known phase relationship between the two clocks.
  • Exceptions: The timing exceptions applied to the CDC (if any) are:
    • None: No Clock Group/False Path/Max Delay Datapath Only timing exceptions exist on the CDC paths. Other timing exceptions such as Multicycle Paths, Min Delay, and Max Delay are not reported by report_cdc.
    • Asynch Clock Groups: The set_clock_groups -asynchronous exception was applied to the CDC clocks.
    • Exclusive Clock Groups: The set_clock_groups -exclusive exception was applied to the CDC clocks.
    • False Path: The set_false_path exception was applied to from/to the CDC clocks or to all CDC paths.
    • Max Delay Datapath Only: The set_max_delay -datapath_only exception was applied to all CDC paths. Note that "Max Delay Datapath Only" is reported when at least one CDC path is only covered by set_max_delay -datapath_only, while all other CDC paths are ignored due to set_false_path constraints.
    • Partial Exceptions: A mix of set_false_path and set_max_delay -datapath_only constraints are applied to some of the CDC paths, and at least one CDC path is normally timed.
  • Endpoints: The total number of CDC path endpoints. This is the sum of Safe, Unsafe, and Unknown endpoints. In this context, an endpoint is a sequential cell input data pin. An FD cell can be counted several times depending on the D, CE, and SET/RESET/CLEAR/PRESET connectivity. For some CDC topologies, only one endpoint is counted while there are effectively several paths crossing the clock domain boundary to reach the CDC structure. For example, in an asynchronous reset synchronizer, several CLEAR pins are connected to the crossing net, but only the first pin of the synchronizer chain is counted.
  • Safe: The number of safe CDC path endpoints. Safe endpoints are endpoints on CDC paths identified as:
    • Asynchronous Clocks with known Safe CDC structures
    • Synchronous Clocks with exceptions and known Safe CDC structures
    • Synchronous Clocks without exceptions that are safely timed regardless of the CDC structure
    • CDC synchronized with HARD_SYNC macro
  • Unsafe: The number of CDC path endpoints that are recognized as having an unsafe structure. The unsafe endpoints are CDC-10, CDC-11, CDC-12 and CDC-13.
    • Combinatorial Logic Topology
    • Fanout Topology
    • Multi-Clock Fan-in Topology
    • non-FD primitive Topology
  • Unknown: The number of unknown CDC path endpoints. No CDC structure can be matched on these endpoints or an unknown CDC circuitry has been detected (CDC-1, CDC-4 and CDC-7).
  • No ASYNC_REG: The number of identified synchronizers that are missing the ASYNC_REG property on at least one of the two first FD cells of the chain.

The following figure shows an example of a Summary by clock pair section.

Figure 1. Summary by Clock Pair Section