power_opt_designstages of the Vivado design flow. Both of these stages occur during implementation, which occurs after the design has been synthesized. If you generate a power optimization report on the synthesized design, the report will only contain information about the power optimization features that were coded into your original design (for example, gating a block RAM using a clock enable (CE)). The report will not detail power optimizations performed later by the tools, during implementation.
To display a Power Optimization Report in the Vivado integrated design environment:
- In the Flow Navigator, select Open Synthesized Design or Open Implemented Design.
- Select The equivalent Tcl command to perform this operation is:
report_power_opt -name <report_name>
- In the Report Power Optimization dialog box, specify the following options.
- Results name
- Specify the name under which the power optimization report appears in the Vivado IDE.
- Export to file
- Check this box to generate a text report in addition to the power optimization report in the Vivado IDE. Specify a file name and location for the text report, and select whether this is a TXT or XML file.
- Open in a new tab
- Check this box to add this new power optimization report to any other
power optimization reports currently displayed in the Vivado IDE. Leave this box unchecked
to replace any power optimization reports currently displayed in the
- Click OK.
A power optimization report appears in the results windows area of the IDE with this new power optimization report.
You can select from different views of the power optimization report.
- General Information
- Information about your design, the Xilinx® device into which your design is implemented, and the Tcl command that generated this power optimization report.
- Count of block RAMs, SRLs, and Slice Registers that were optimized by the user in the design and by the power optimization tool.
- Things you can do to further optimize your design for power.
- Hierarchical Information
- Details of the block RAMs, SRLs, and Slice Registers for which Vivado has performed power optimization.