Experiment Using the Vivado Power Optimizer Feature - 2020.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2020.2 English

To maximize power savings when you run the power optimizer in the Vivado® tools, you should run power optimization on the entire design and not exclude portions of the design. If you do not see anticipated power savings after enabling power optimization, the three areas of potential debug are the global set and reset signals, block RAM enable generation, and register clock gating. A low number of power optimization generated enables in this area could indicate the need to review coding practices or options/properties set for design synthesis and implementation.

Note: In the Vivado tools, power optimization works to minimize the impact on timing while maximizing power savings. However, in certain cases, timing may degrade after power optimization. For techniques to offset this impact, see Preserving Timing After Power Optimization.
Global set and reset signals
Where possible, minimize the use of asynchronous set/reset signals especially to datapath or pipeline flip-flops as well as block RAMs. You should also consider constraining the global set and reset signals as dont_touch during the power_opt_design step to avoid their use as enables. Note that setting the dont_touch property in HDL will cause every step in the flow to obey this property. It is recommended that this option is set up as an XDC constraint only for the power optimization step. Here is an example of how to do this:
set_property DONT_TOUCH true [get_cells u1]
Finally, ensure that the signal rate and probabilities of the global set and reset signals are set correctly prior to running power optimizer and vectorless power estimation.
Slice registers and SRLs
A number of different reasons could explain why power_opt_design might not be able to generate clock enables for slice registers or SRLs in the design. Some examples are:
  • Having combinational loops in the design
  • Using set/reset signals at the flip-flops and SRLs that are sourced from primary inputs to the design
  • Using asynchronous set/reset signals at the datapath flip-flops
  • Large number of clock domains in the design preventing enables being generated due to clock domain crossing issues
  • SRL sizes: Typically the larger the number of shift register stages in the SRLs, the more difficult it is to generate a single clock enable for all stages
Block RAMs
Block RAM rich designs are excellent candidates for power savings. Vivado uses a variety of optimization techniques to generate enables and save power. If block RAM gating coverage is low after using power_opt_design, some of the possible reasons could be:
  • BRAMs are mainly FIFO18/FIFO36 cells. These cannot be optimized by the tool.
  • Memories inferred or instantiated are mainly in true dual port (TDP) mode using asynchronous clocks on their A and B ports that cannot be optimized by power_opt_design.
  • Use of asynchronous reset signals to either the block RAMs themselves or to the address/write-enable flip-flops feeding the block RAMs.