Preserving Timing After Power Optimization - 2020.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2020.2 English

Power optimization works to minimize the impact on timing while maximizing power savings. However, in certain cases, if timing degrades after power optimization, you can employ a few techniques to offset this impact.

Where possible, identify and apply power optimizations only on non-timing critical clock domains or modules using the set_power_opt XDC command. If the most critical clock domain happens to cover a large portion of the design or consumes the most power, review critical paths to see if any cells in the critical path were optimized by power optimization. Note that objects optimized by power optimization have an IS_CLOCK_GATED property on them. Exclude these cells from power optimization. To locate clock gated cells, you can use the following Tcl command:

get_cells -hier -filter {IS_CLOCK_GATED==1}

You can use the Find dialog box to locate these cells as shown in the following figure.

Figure 1. Finding Power Optimized Cells

A simpler alternative is to limit power optimization to block RAMs. This minimizes the timing impact but its effectiveness is dependent on the number of block RAMs present in the design and how effectively they have been gated. To limit power optimization to block RAMs, run a set_power_opt -cell_types {bram} command before running the opt_design or power_opt_design commands.