Generating an IBERT Core using the Vivado IP Catalog - 2020.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2020-12-07
Version
2020.2 English

The first phase of getting a suitable hardware design to help debug and validate your system's high-speed serial I/O interfaces is to generate the IBERT core. The following steps outline how to do this:

  1. Open the Vivado IDE.
  2. On the first panel, choose Manage IP > New IP Location, then click Next when the Open IP Catalog wizard opens.
  3. Select the desired part, target language, target simulator, and IP location. Click Finish.
  4. In the IP Catalog under Debug and Verification > Debug, you will find one or more available IBERT cores as shown in the following figure, depending on the device selected in the previous step.
  5. Double-click the desire IBERT architecture to open the Customize IP Wizard for that core.

Customize the IBERT core for your given hardware system requirements. For details on the various IBERT cores available, see the following IP Documents:

  • Integrated Bit Error Ratio Tester 7 Series GTX Transceivers LogiCORE IP Product Guide (PG132)
  • Integrated Bit Error Ratio Tester 7 Series GTP Transceivers LogiCORE IP Product Guide (PG133)
  • Integrated Bit Error Ratio Tester 7 Series GTH Transceivers LogiCORE IP Product Guide (PG152)