The Integrated Logic Analyzer (ILA) feature allows you to perform in-system debugging of post-implemented designs on an FPGA or Versal™ device. This feature should be used when there is a need to monitor signals in the design. You can also use this feature to trigger on hardware events and capture data at system speeds.
The ILA core can be instantiated in your RTL code or inserted post synthesis in the Vivado design flow. In-System Logic Designs and Debugging Logic Designs in Hardware of this guide have more details on the ILA core and its usage methodology in the Vivado® Design Suite. Detailed documentation on the ILA core IP can be found in the Integrated Logic Analyzer LogiCORE IP Product Guide (PG172).