PCI Express Link Debug - 2020.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2020-12-07
Version
2020.2 English

The Versal PCI Express® Integrated Block in Vivado supports link debug. If enabled, the core will store the Link Training and Status State Machine (LTSSM) state transitions which is accessible in the Vivado Hardware Manager.