Programming the Hardware Device - 2020.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2020-12-07
Version
2020.2 English

Once the programming file has been associated with the hardware device, you can program the hardware device using by right-clicking on the device in the Hardware window and selecting the Program Device menu option. You can also use the program_hw_device Tcl command. For instance, to program the first device in the JTAG chain, use the following Tcl command:

program_hw_devices [lindex [get_hw_devices] 0]

Once the progress dialog has indicated that the programming is 100% complete, you can check that the hardware device has been programmed successfully by examining the DONE status in the Hardware Device Properties view.

Figure 1. Checking the DONE Status of an FPGA or Versal Device

You can also use the get_property Tcl command to check the DONE status. For instance, to check the DONE status of a Kintex®-7 device that is the first device in the JTAG chain, use the following Tcl command:

get_property REGISTER.IR.BIT5_DONE [lindex [get_hw_devices] 0]

On Versal devices, the command will differ slightly as the DONE status register is different. Index 1 will need to be read as the first device returned by get_hw_devices and will be the arm_dap in a single device use case.

get_property REGISTER.JTAG_STATUS.BIT[34]_DONE [lindex [get_hw_devices] 1]

If you use another means to program the hardware device (for instance, a flash device or external device programmer), you can also refresh the status of a hardware device by right-clicking the Refresh Device menu option or by running the refresh_hw_device Tcl command. This refreshes the various properties for the device, including but not limited to the DONE status.

Important: For non-Versal architectures, if your design contains debug cores, ensure that the JTAG clock is 2.5x times slower than the debug hub clock.
Important: User SCAN Chain: For non-Versal architectures,Vivado Programmer tries to detect debug cores on the user scan chain specified in the design by default. It does the detection by issuing a JTAG_CHAIN 1 command to the device. If you have programmed a device with a design that does not have any debug cores or a debug core with a user scan chain of 2, 3, or 4, you will see a warning.
Important: User SCAN Chain: Each Versal device Control, Interfaces and Processing System (CIPS) BSCAN port corresponds to a different user scan chain. By default the Vivado programmer will only scan user scan chains 2 and 4 when scanning for MicroBlaze Debug Module (MDM) cores. If a MicroBlaze Debug Module is connected to either BSCAN_0 or BSCAN_2 ports on the CIPS, the user mask will need to be updated to include these scan chains as demonstrated below.

To determine the user scan chain setting, for non-Versal architectures, open the implemented design and use:

get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]

You can change the user scan chain used in the Vivado Hardware Manager. Note that the BSCAN_SWITCH_USER_MASK is a bit mask value. See the following figure.

Alternatively you can specify the user scan chain value as an option to hw_server start-up.

hw_server -e "set bscan-switch-user-mask <user-bit-mask>"
Figure 2. BSCAN Switch User Mask

Tip: For designs prior to Vivado 2016.3 Xilinx recommends manually launching hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.