The Debug Bridge IP can be used in both flat and Dynamic Function eXchange designs. Below are the details on the Debug Bridge configurations used in the static or Reconfigurable Partition (RP) region of a Dynamic Function eXchange design. Multiple Debug Bridge instances are permitted in a partition depending on the design requirements.
- BSCAN Primitive
- This mode is used when a Debug Bridge containing a BSCAN primitive is required in the static region. The BSCAN master interface of this Debug Bridge can be connected to another Debug Bridge instance in the static and/or PR region(s) providing one or more communication pathways for debugging those regions.
- From BSCAN to Debug Hub
- In this mode, the Debug Bridge uses the BSCAN slave interface to communicate
to Vivado Hardware Manager. It uses the Debug Hub interface to communicate
with the design cores within the relevant static or RP region. You can also
optionally add additional BSCAN Masters to the output of this Debug Bridge,
which enables debugging other debug cores like MicroBlaze Debug Module (MDM)
or other Debug Bridge instances. Note: The tool automatically connects the debug cores in an RP to the Debug Bridge if this is the only Debug Bridge instantiated in the partition.
- From AXI to BSCAN
- In this mode, the Debug Bridge receives XVC Commands via AXI4-Lite slave interface. This Debug Bridge can further communicate with other debug cores/ Debug Bridge instances in the design via the Soft-BSCAN (Boundary Scan) master interface. The Soft BSCAN interface enables extension of the JTAG interface to internal USER defined scan chains/Debug Bridge instances.
- From JTAG to BSCAN
- In this mode, the Debug Bridge receives XVC Commands via JTAG slave interface driven by user logic. This Debug Bridge can further communicate with other debug cores/ Debug Bridge instances in the design via the Soft-BSCAN (Boundary Scan) master interface. The Soft BSCAN interface enables extension of the JTAG interface to internal USER defined scan chains/Debug Bridge instances.
- From PCIe to BSCAN
- In this mode, the Debug Bridge receives XVC Commands via PCIe Extended
Configuration slave interface. This Debug Bridge can further communicate
with other debug cores/ Debug Bridge instances in the design via the
Soft-BSCAN (Boundary Scan) interface. The Soft BSCAN master interface
enables extension of the JTAG interface to internal USER defined scan
chains/Debug Bridge instances. Note: This mode is only available for UltraScale+™ and UltraScale™ device architectures
- From PCIe to JTAG
- In this mode, the Debug Bridge receives XVC Commands via PCIe Extended
Configuration interface. This Debug Bridge brings out the JTAG pins out of
the FPGA through I/O pins. This mode is mainly used to debug design on
another board over XVC. Note: This mode is only available for UltraScale+™ and UltraScale™ device architectures.
- From AXI to JTAG
- In this mode, the Debug Bridge receives XVC commands via AXI4-Lite interface to send over the JTAG pins to a target device.