Using Vivado Logic Analyzer to Debug the Design - 2020.2 English

The Vivado® logic analyzer feature is used to interact with new ILA, VIO, and JTAG-to-AXI Master debug cores that are in your design. To access the Vivado logic analyzer feature, click the Open Hardware Manager button in the Program and Debug section of the Flow Navigator.

The steps to debug your design in hardware using an ILA debug core are:

1. Connect to the hardware target and program the FPGA or ACAP with the .pdi file.
2. Set up the ILA debug core trigger and capture controls.
3. Arm the ILA debug core trigger.
4. View the captured data from the ILA debug core in the Waveform window.
5. Use the VIO debug core to drive control signals and/or view design status signals.
6. Use the JTAG-to-AXI Master debug core to run transactions to interact with various AXI slave cores in your design.