The Virtual Input/Output (VIO) debug feature can both monitor and drive internal FPGA or Versal ACAP signals in real time. In the absence of physical access to the target hardware, you can use this debug feature to drive and monitor signals that are present on the real hardware.
This debug core needs to be instantiated in the RTL code, hence you need to know up-front, what nets to drive. The IP Catalog lists this core under the Debug category. Debugging Logic Designs in Hardware of this guide has more details on the VIO core and its usage methodology in the Vivado Design Suite. Detailed documentation on the VIO core IP can be found in the Virtual Input/Output LogiCORE IP Product Guide (PG159).