Versal™
ACAPs no longer require the
generation of IBERT IP as the necessary logic required to use in-system Serial I/O debug
is now integrated into the GTY transceiver architecture. Any design that utilizes the
GTY transceivers can be used for Serial I/O Hardware Debugging. The Versal Serial I/O Hardware Debugging Flow has two distinct
phases:
- Design Creation: Customizing and generating a design that utilizes the devices GTY transceivers, typically using the Versal ACAPs transceivers wizard.
- Serial I/O Analysis phase: Interacting with the GTY transceivers in the design using the Vivado® Hardware Manager to debug and verify issues in your high-speed serial I/O links.