Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal™ ACAP design process Design Hubs can be found on the Xilinx.com website. This document covers the following design processes:
- Hardware, IP, and Platform Development
-
Creating the PL IP blocks for the hardware
platform, creating PL kernels, subsystem functional
simulation, and evaluating the
Vivado®
timing,
resource use, and power closure. Also involves
developing the hardware platform for system
integration. Topics in this document
that apply to this design process include:
- Using the Netlist Insertion Method to Debug a Design
- Using the HDL Instantiation Method to Debug a Design
- Using a VIO Core to Debug a Design in Vivado Design Suite
- Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a Design
- Using the Vivado Logic Analyzer to Debug Hardware
- Using the ECO Flow to Replace Debug Probes Post Implementation
- Debugging Designs Using the Incremental Compile Flow
- Using the Vivado ILA Core to Debug JTAG-AXI Transactions
- Board System Design
- Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. Topics in this document that apply to this design process include: