Step 1: Generating a Zynq UltraScale+ MPSoC PS Xilinx Support Archive - 2020.2 English

1. Open the Vivado IDE.
2. Click Create Project, and click Next.
   
   
3. Set your project name, and specify the project directory. Click Next.
4. Select Project type as RTL project.
5. Select do not specify sources at this time checked, then click Next.
6. To choose the board, click the board icon, and select Zynq UltraScale+ ZCU102 Evaluation board, with Board Rev 1.0. Click Next.
   
   
7. The project summary displays. To create the project, click Finish.
8. In the Flow Navigator, select Create Block Design. You can specify the design name and directory, but it is not necessary for a local project directory. Click OK to create the block design.
   
   
9. An empty design diagram displays. Click the Add IP button to add IP. Select the IP based on the selected board (for the ZCU102 evaluation board, search for Zynq UltraScale+ MPSoC) and double-click the selected IP.
   
   
10. In the design diagram window, select Run Block Automation. Click OK to continue creating the ZCU102 design.
    
    
11. When the design diagram appears, use the following steps to validate the design:
    1. Connect maxihpm0_fpd_aclk and maxihpm1_fpd_aclk together to pl_clk0, as shown in the following figure.
       1. Select maxihpm0_fpd_aclk and drag it to maxihpm1_fpd_aclk.
       2. Select maxihpm1_fpd_aclk and drag it to pl_clk0.
    2. Right-click the Zynq UltraScale+ MPSoC block and select Validate Design to validate the design. It will say validation successful. Click OK.
       
       
12. Customize the design by double-clicking the Zynq UltraScale+ MPSoC block and configuring the parameters. There are four valid GT configurations for ZCU102 board as shown in the following table.

    Table 1. Supported PS-GTR Connector Functionality

    SEL (S3,2,1,0)	ICM Settings (Lane 0,1,2,3)	PCIe Connector	DP Connector	USB Connector	SATA Connector
    0 0 0 0	PCIe.0, PCIe.1, PCIe.2, PCIe.3	PCIe Gen2 x4	N.C.	N.C.	N.C.
    1 1 1 1	DP.1, DP.0, USB, SATA	N.C.	DP.0, DP.1	USB0	SATA1
    1 1 0 0	PCIe.0, PCIe.1, USB, SATA	PCIe Gen2 x2	N.C.	USB0	SATA1
    1 1 1 0	PCIe.0, DP.0, USB, SATA	PCIe Gen2 x1	DP.0	USB0	SATA1

13. Select the settings based on your requirements by double-clicking theZynq UltraScale+ MPSoC block to customize GT Lane configuration.
14. Select I/O Configuration > High Speed. Select one of the four combinations using the settings in the following screenshots.
    1. PCIe – Display Port - USB - SATA (Default Vivado preset)
       
       
    2. PCIe–PCIe - USB - SATA
       
       
    3. Display Port – Display Port - USB - SATA
       
       
    4. PCIe–PCIe - PCIe - PCIe (PCIe x4)
       
       
15. Click OK when finished customizing the GT Lane configuration.
16. Do not click Run Block Automation again, even though the banner will reappear. If used, the customized values will reset.
17. Click the Sources tab on the top left of the Block Design window.
    1. Under the Block Designs group, click IP Sources.
    2. Right-click design_1 and then click Create HDL Wrapper.
    
    
    
18. Leave the option Let Vivado manage wrapper and auto-update selected. Click OK in the dialog to create the HDL wrapper.
19. Right-click design_1_i in the IP Sources tab, and click Generate Output Products.
20. Click Generate to generate with the default options in the panel.
21. After the generation is complete, click OK.
22. Select File > Export > Export Hardware.
    
    
23. In the Export Hardware Platform wizard, select a Fixed platform type. Click Next.
24. On the next page, select Pre-Synthesis for the platform output type.
25. Leave the XSA name as design_1_wrapper, and choose a location to store the exported XSA, preferably in a new directory.