- In the Flow Navigator, under Program and Debug, click Generate Bitstream.
- In the Save Project dialog box click Save. If a dialog box appears indicating this will cause the Synthesis results to go out of date, click OK. This applies the MARK_DEBUG attributes on the newly marked nets. You can see those constraints by inspecting the sinegen_demo_kc705.xdc file.
- When the No Implementation Results Available dialog box pops up, click Yes. In the Launch Runs dialog box, accept all of the default settings (Launch runs on local host) and click OK.
- When the bitstream generation completes, the Bitstream Generation Completed dialog box pops up. Click OK.
- In the dialog box asking you to closetye synthesized design before opening the implemented design. Click Yes.
- Examine the Timing Summary report to ensure that all the specified timing
constraints are met.
Proceed to Using the Vivado Logic Analyzer to Debug Hardware to complete the rest of the steps for debugging the design.