Adding Sine Mid - 2020.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2021-01-21
Version
2020.2 English
  1. In the IP catalog, double-click the DDS Compiler IP a second time.
  2. Specify the following on the Configuration tab:
    • Component Name: type sine_mid
    • Configuration Options: select SIN COS LUT only
    • Noise Shaping: select None
    • Under Hardware Parameters, set the Phase Width to 8, and the Output Width to 18
  3. On the Implementation tab, set the Output Selection to Sine.
  4. On the Detailed Implementation tab, set Control Signals to ARESETn (active-Low).
  5. Select the Summary tab, review the settings and click OK (Following figure).

    When the sine_mid IP core is added to the design, the Generate Output Products dialog box displays to generate the output products required to support the IP in the design.

  6. Click Generate to generate the default output products for sine_mid. A dialog box opens saying that the Out of context module run was launched for generating output products. Click OK.