- Create a new Vivado RTL project in 2020.2, targeting to the required device.
- Add the directories
verifto the project by clicking on the + button.
- Mention the UVM verification files for simulation only.
- After the hierarchy is updated, ensure to select adder_4_bit_tb_top.sv file as top module.
- For UVM, you need to provide test name, here the test name is
adder_4_bit_basic_test. For this add
-testplusarg UVM_TESTNAME=adder_4_bit_basic_test -testplusarg UVM_VERBOSITY=UVM_LOWto
- Launch simulation. This can run simulation for 1000 ns by default. Click run all .You can see following in TCL console.
Following are the steps to use UVM in Non-Project/Batch Mode:
- To run the simulation in non-project mode, change the current working directory to the run folder. cd ./Adder_4_bit/run
- For standalone simulation in Vivado you
run_xsim.cshon Linux and
run_xsim.baton windows or source
run.tclusing the below command in Linux/Windows. Vivado
–mode batch –source run.tcl
- Once the simulation gets finished you can observe the UVM test results in
the Shell or command prompt as shown in the following figure.
Directory Structure of both project and non project mode:
- src & verif - Design and verification environment related files.
- Run - Location to run simulation in Non project mode.
- UVM_test - Project Mode XSIM simulation.
Note: If you are running your design in the command line mode and want to use UVM, add