Creating the Vivado Simulator Project File - 2020.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2021-01-21
Version
2020.2 English

A Vivado® simulator project script specifies design source files and libraries to parse and compile for simulation. This method is useful to create a simulation project script that can be run repeatedly over the course of project development.

The format for a Vivado simulator project script (prj file) is as follows:

verilog | vhdl| sv <library_name> {<file_name>.v|.vhd|.sv

where,

  • verilog | vhdl | sv specifies whether the design source is a Verilog, VHDL, or SV file.
  • <library_name> specifies the library into which you may compile the source file. If unspecified, the default library for compilation is work.
  • <file_name>.v|.vhd|.sv specifies the name of the design source file to compile.
Important: While you can specify one or more Verilog source files on a single command line, you can only specify one VHDL source on a single command line.

In this step, you build a Vivado simulator project script by editing an existing project script to add missing source files. The command lines for the project script should be constructed using the syntax described above.

  1. Browse to the <Extract_Dir>/scripts folder.
  2. Open the simulate_xsim.prj project script with a text editor.
  3. Add the following commands to the project script:
    vhdl xil_defaultlib "../sources/sinegen.vhd"
    vhdl xil_defaultlib "../sources/debounce.vhd"
    vhdl xil_defaultlib "../sources/fsm.vhd"
    vhdl xil_defaultlib "../sources/sinegen_demo.vhd"
    verilog xil_defaultlib "../sim/testbench.v"
  4. Save and close the file.

You do not need to list the sources based on any specific order of dependency. The xelab command resolves the order of dependencies, and automatically processes the files accordingly.

Tip: For your reference, a completed version of the tutorial files can be found in the ug937-design-files/completed folder.