Locating Tutorial Design Files - 2020.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)
Document ID
UG937
Release Date
2021-01-21
Version
2020.2 English
There are separate project files and sources for each of the labs in this tutorial. You can find these at the link provided below or under Support > Documentation > Development Tools (Product Type) > Hardware Development (Product Category) > Vivado Design Suite – HLx Editions (Product) > Tutorials (Doc Type) on the Xilinx website.
  1. Download the reference design files.
  2. Extract the zip file contents into any write-accessible location.

    This tutorial refers to the extracted file contents of ug937-design-files directory as <Extract_Dir>.

Recommended: You modify the tutorial design data while working through this tutorial. Use a new copy of the design files each time you start this tutorial.

The following table describes the contents of the ug937-design-files.zip file.

Table 1. Design File Contents
Directories/Files Description
/completed Contains the completed files, and a Vivado 2020.x project of the tutorial design for reference.

(x denotes the latest version of Vivado 2020 IDE)
/scripts Contains the scripts you run during the tutorial.
/sim Contains the testbench.v file.
/sources Contains the HDL files necessary for the functional simulation.
readme.txt readme.txt is a readme file about the contents and version history of this tutorial design.
/uvm UVM example needed for Lab 5