Step through the source code line-by-line and examine how the low frequency wave is selected, and whether the DDS compiler output is correct.
- On the Vivado simulator toolbar menu,
click the Step button .
The simulation steps forward to the next executable line, in this case in another source file. The fsm.vdh file is opened in the Text Editor. You may need to relocate the Text Editor to let you see all the windows as previously arranged.Note: You can also type the
stepcommand at the Tcl prompt.
- Continue to Step through the design, until the code returns to line 144 of
You have stepped through one complete cycle of the circuit. Notice in the Waveform window that while
selis 0, signal
sine_lis assigned as a low frequency sine wave to the output sine. Also, notice that
- For debug purposes, initialize the value of
sine_lby entering the following add_force command in the Tcl console:
add_force /testbench/dut/U_SINEGEN/sine_l 0110011011001010
This command forces the value of
sine_linto a specific known condition, and can provide a repeating set of values to exercise the signal more vigorously, if needed. Refer to the Vivado Design Suite User Guide: Logic Simulation (UG900) for more information on using
- Continue the simulation by clicking the Run All
a few more times.
In the Waveform window, notice that the value of
sine_l[15:0]is now set to the value specified by the add_force command, and this value is assigned to the output signal
sine[19:0]since the value of
selis still 0.
sine_lsignal in the HDL source files, and identify the input for
- In the Text Editor, right-click to open the popup menu, and select the
Find in files option to search for
- Select the Match whole word and
Enabled design sources checkboxes, as
shown in the following figure, and click Find.
The Find in Files results display at the bottom of the Vivado IDE, with all occurrences of
sine_lfound in the sinegen.vhd file.
- Expand the Find in Files results to view the results in the
The second result, on line 111, identifies a problem with the design. At line 111 in the sinegen.vhd file, the
m_axis_data_tdata_sine_lowsignal is assigned to
sine_l. Since line 111 is commented out, the
sine_lsignal is not connected to the low frequency DDS compiler output, or any other input.
- Uncomment line 111 in the sinegen.vhd file, and click the Save File button .
- In the Tcl Console, remove the force on