In this lab, you run the following steps:
- Logic optimization:
- Physical synthesis:
- Bitstream generation:
For a complete description of each of these steps, see Vivado Design Suite User Guide: Implementation (UG904).
Between each of these steps, you can generate reports, and write checkpoints to save the design in different stages of implementation.
Before launching implementation, you must read the design constraints that are only used in implementation. The XDC file, top_physical.xdc, contains physical constraints that are used in implementation, but do not apply to synthesis.
In this case, these constraints could have been read into the in-memory design prior to synthesis, because synthesis ignores them; however, this file could also contain different timing constraints, not to be used in synthesis, that must be read in after synthesis and just prior to implementation.
- Add the following line to your Tcl
- Add optimization and placement commands to your Tcl
opt_design place_design write_checkpoint -force post_place.dcp report_timing -file timing_place.rpt
After placement completes, your script writes a post-placement checkpoint and create a custom timing report, which provides a detailed timing report for the single worst timing path in the design.
- Add physical synthesis and routing commands to your Tcl
phys_opt_design route_design write_checkpoint -force post_route.dcp report_timing_summary -file timing_summary
After routing completes, your script writes a post-routing design checkpoint and creates a timing summary report.
- Finally, write out a bitstream by adding the
write_bitstream -force sys_integration_top.bit
This is the complete Non-Project Mode design flow for implementing a design from RTL source files, including designing with IP, through bitstream generation.