In this step, you will define additional physical constraints to the design, such as
The I/O Planning view layout displays the Package window, as well as the I/O Ports and Package Pins windows, to facilitate planning the I/O port assignment for the design.
For the purposes of this tutorial, assume the PCB layout has been completed, and therefore certain pins are not accessible on the FPGA package. You can prohibit the Vivado tool from using these pins during placement and routing (assuming you have not already specified all of your I/O assignments).
to open the I/O Planning view layout from the Layout Selector in
the tool bar menu.
- Select the AA8 pin in the Package
window. Tip: Use the X and Y-axis values on the edge of the Package window to help you locate this pin on the package. You may need to zoom in or enlarge the Package window to make the values visible.
- With the pin selected, right-click and select Set
When you unselect the pin, you will notice the site now has a red circle with a diagonal line through it, indicating that it is unusable.
- Look at the Tcl Console and review the Tcl command produced by the Vivado
startgroup set_property prohibit 1 [get_bels IOB_X1Y34/PAD] set_property prohibit 1 [get_sites AA8] endgroup