Tutorial Design Description - 2020.2 English

Vivado Design Suite Tutorial: Using Constraints (UG945)

Document ID
UG945
Release Date
2021-02-08
Version
2020.2 English

The sample design used throughout this tutorial consists of a small design called project_cpu_netlist. There is a top-level EDIF netlist source file, as well as an XDC constraints file.

The design targets an XC7K70T device. A small design is used to allow the tutorial to be run with minimal hardware requirements and to enable timely completion of the tutorial, as well as to minimize the data size.