- If not done in the prior section: In the Vivado Hardware Manager, refresh the device to
find all the Vivado Debug cores.
There are three ILA cores, one VIO core and one MIG core in this design.
- If not done in the prior section: In one of the ILA core windows, click the Specify the probes file links to find Bitstreams/top_count_up_shift_right.ltx.
- Click OK then Refresh.
- In hw_ila_2, click the + to add probes in the Trigger Setup window.
- Select icap_err_inserted and click OK.
- Set the trigger in the Trigger Settings window to rising edge of icap_error_inserted.
- Set the trigger position in the Settings window to 512. Figure 1. Trigger Setting for icap_err_inserted
- Push the Run Trigger button in Hardware Manager GUI.
- In the UART terminal, set Reconfig Type as Normal CRC from DDR4 (option 7). This is the default setting.
- Push the center pushbutton – this inserts the CRC error – and then reconfigure the module you would like via pushbutton or the UART terminal. The CRC value at the end of the partial bitstream is swapped to cause a CRC error. As a result, INIT_B goes low (the INIT_B LED turns red), indicating a CRC error. Notice on the board that the function not reconfigured is still operating.
- In ILA Waveform, the trigger location marks where icap_err_inserted is
asserted. After the error insertion, you will see PRERROR then PRDONE goes high.
rm_decouplesignal is high throughout, indicating the Reconfigurable Partition is still isolated.Figure 2. Waveform Capture Showing icap_err_inserted, PRERROR, PRDONE, and Decouple Asserted
Note: The dfxc_vsm_vs_*_event_error signal is low, but it will be pulsed outside of captured waveform because of the latency in Dynamic Function eXchange (DFX) Controller.
If the CRC error is found using the standard CRC, which only occurs at the end of the partial bitstream, the incorrect bitstream has already been loaded into the device. There is no way to know where any incorrect bits exist, or if they will disrupt the reconfigurable or static design. The only way to be sure of a full recovery from this condition is to perform a full reconfiguration of the device. In this tutorial, only the CRC value is swapped, so we can be assured that the error has not affected the static design.
- When CRC error occurred, the DFX Controller entered shutdown mode. In the
UART terminal, Report Status (option 9) shows the RP is in shutdown mode and it
reports a BS ERROR. To recover from this error status, return the RP to active
mode by selecting Put RPs in Active Mode (option 5) from the terminal, and
reconfigure with a correct partial bit file. Then INIT_B returns high (LED turns
green) and the design is now back to normal operation.
Next, try with per-frame CRC values inserted.
- In the terminal, set the Reconfig Type to per Frame CRC (option 7).
- In the Hardware Manager, re-arm the trigger by clicking the Run Trigger button. Then perform Dynamic Function eXchange from the terminal or via pushbutton.
- In the ILA waveform, you can see the error has been inserted in the first frame of partial bitstream – you can see that reconfiguration starts soon after vs_rm_*_decouple goes High. However, when using per-frame CRC, the error inserted frame has not been loaded into the device yet, so there is no need for a reconfiguration of the full design, just reconfigure the incomplete Reconfigurable Partition with a valid partial bitstream. To recover from the error status, repeat the procedure from step 8.
Partial bitstreams with and without per-frame CRC checking were created and loaded into the QPSI flash as part of the PROM file. The design can insert CRC failures by swapping some bits in the CRC value just prior to loading the file into the ICAP. Any uncompressed – using bitstream generation property, not the DFX Controller feature – partial bitstream can have an error injected in this manner to see how the device responds. This is controlled via the center pushbutton.