The Vivado software tool flow lets you compile DFX designs using an in-context methodology. This solution requires multiple passes through place and route. The first pass establishes the static design implementation result (along with the first Reconfigurable Module (RM) for each Reconfigurable Partition (RP)). Then all subsequent place and runs are done in context with that initial static image. A fully routed and locked static design database, containing netlist, placement, and routing information for the entire static region, must be loaded into Vivado before implementing any RMs beyond the first.
The Abstract Shell solution reduces the requirements for this in-context flow. Because the static design is locked, it cannot (and must not) be modified when new RMs are implemented. The context is still critical, so the path through the tools does not change. However, instead of loading a full static design image, an Abstract Shell checkpoint is used. This Abstract Shell contains only a minimal logical and physical database necessary to implement a new RM within a specific RP to validate timing and pass PR Verify, and then generate a partial bitstream for that RM.
This lab uses the DFX Controller IP design shown in Lab 7. The first pass through place and route is identical to the run completed in Lab 7, but then all child runs to implement new RMs are done within Abstract Shells. The end result is a collection of design checkpoints that can be used to program the VCU118 in the same way that was done in Lab 7, but compilation time for producing the child RMs is reduced.