Block-Level Synthesis Strategy - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

With Vivado synthesis, you can use various strategies and global settings to customize how the design is synthesized. In most cases, these options are global and affect the entire design. You can use the block-level synthesis strategy to synthesize different levels of hierarchy with different global options in a top-down flow. This flow is faster and easier to perform than a bottom-up compile. You can set constraints for the full design rather than setting constraints for a lower level and then resetting for the top level.

Set the block-level synthesis strategy in the XDC file using the following syntax:

set_property BLOCK_SYNTH.<option_name> <value> [get_cells <instance_name>]


  • <option_name> is the option to be set.
  • <value> is the value to be assigned to the option.
  • <instance_name> is the hierarchical instance on which to set the option.
Note: These properties are always set on hierarchical instances. This allows modules or entities that are instantiated more than once to be synthesized with different options.

For example, you can set the following strategies in an XDC file:

set_property BLOCK_SYNTH.RETIMING 1                 [get_cells U1]
set_property BLOCK_SYNTH.STRATEGY {AREA_OPTIMIZED}  [get_cells U2]
set_property BLOCK_SYNTH.STRATEGY {AREA_OPTIMIZED}  [get_cells U3]
set_property BLOCK_SYNTH.STRATEGY {DEFAULT}          [get_cells U3/inst1]

Vivado synthesis is performed as shown in the following figure.

Figure 1. Block-Level Synthesis Strategy Example

You can set multiple BLOCK_SYNTH properties on the same instance to experiment with different options. For example:

set_property BLOCK_SYNTH.FSM_EXTRACTION {OFF} [get_cells inst]

When working with IP, you can use the block-level synthesis strategy as follows:

  • If the IP is compiled globally, you can use this strategy on the top level of the IP.
  • If the IP is out-of-context, you cannot use the strategy, because the IP appears as a black box. Instead, use global settings when compiling the IP.
Note: For more information on this feature and the supported strategies and options, see the Vivado Design Suite User Guide: Synthesis (UG901).