Before looking at the timing results to see if there are any violations, be sure that every synchronous endpoint in your design is properly constrained.
check_timing to identify unconstrained paths. You can run this command as a standalone command, but it is also part of
report_timing_summary. In addition,
report_timing_summary includes an Unconstrained Paths section where N logical paths without timing requirements are listed by the already defined source or destination timing clock. N is controlled by the
After the design is fully constrained, run the
report_methodology command and review the TIMING and XDC checks to identify non-optimal constraints, which will likely make timing analysis not fully accurate and lead to timing margin variations in hardware.