Checking for Positive Timing Slacks - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

The following timing metrics indicate timing violations. Numbers must be positive to meet timing.

  • Setup/Recovery (max delay analysis): WNS > 0 ns and TNS = 0 ns
  • Hold/Removal (min delay analysis): WHS > 0 ns and THS = 0 ns
  • Pulse Width: WPWS > 0 ns and TPWS = 0 ns