Clock Exceptions Precedence Over set_max_delay - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

When writing the CDC constraints, verify that the precedence is respected. If you use set_max_delay -datapath_only on at least one path between two clocks, the set_clock_groups constraint cannot be used between the same clocks, and the set_false_path constraint can only be used on the other paths between the two clocks.

In the following figure, the clock clk0 has a period of 5 ns and is asynchronous to clk1. There are two paths from the clk0 domain to the clk1 domain. The first path is a 1-bit data synchronization. The second path is a multi-bit gray-coded bus transfer.

Figure 1. Multiple Interactions Between Two Asynchronous Clocks

The designer decides that the gray-coded bus transfer requires a Max Delay Datapath Only to limit the delay variation among the bits, so it becomes impossible to use a Clock Groups or False Path constraint between the clocks directly. Instead, two constraints must be defined:

set_max_delay -from [get_cells GCB0[*]] -to [get_cells [GCB1a[*]] \
-datapath_only 5
set_false_path -from [get_cells REG0] -to [get_cells REG1a]

There is no need to set a false path from clk1 to clk0 because there is no path in this example.