Identifying Timing Violations Root Cause - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

For setup, you must first analyze the worst violation of each clock group. A clock group refers to all intra, inter, and asynchronous paths captured by a given clock.

For hold, all violations must be reviewed as follows:

  • Before routing, review only violations over 0.5 ns.
  • After routing, start with the worst violation.