MAX_FANOUT - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

MAX_FANOUT forces the synthesis to replicate logic to meet a fanout limit. The tool is able to replicate logic, but not inputs or black boxes. Accordingly, if a MAX_FANOUT attribute is placed on a signal that is driven by a direct input to the design, the tool is unable to handle the constraint.

Take care to analyze the signals on which a MAX_FANOUT is placed. If a MAX_FANOUT is placed on a signal that is driven by a register with a DONT_TOUCH or drives signals that are in a different level of hierarchy when the DONT_TOUCH attribute is on that hierarchy, the MAX_FANOUT attribute will not be honored.

Synthesis appends the replicated cells with _rep for the first replication and subsequent replications are _rep__0, _rep__1 and so on. These cells can be seen in the post synthesized netlist by selecting Edit > Find on cells.

Important: Use MAX_FANOUT sparingly during synthesis. The place_design and phys_opt_design commands in the Vivado® tools perform placement-based replication, which is more effective than logical replication in synthesis. If a specific fanout is desired, it is often worth the time and effort to manually code the extra registers.