Additional I/O pin planning steps are required when using Xilinx Memory IP. After the IP is customized, assign the top-level IP ports to physical package pins in either the elaborated or synthesized design in the Vivado IDE. All of the ports associated with each Memory IP are grouped together into an I/O Port Interface for easier identification and assignment. A Memory Bank/Byte Planner is provided to assist you with assigning Memory I/O pin groups to byte lanes on the physical device pins. For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
Take care when assigning memory interfaces and try to limit congestion as much as possible, especially with devices that have a center I/O column. Bunching memory interfaces together can create routing bottlenecks across the device. The Zynq-7000 SoC and 7 series Devices Memory Interface Solutions (UG586) and the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) contain design and pinout guidelines. Be sure that you follow the trace length match recommendations in these guides, verify that the correct termination is used, and validate the pinout in by running the DRCs after memory IP I/O assignment. For more information on memory interface signal termination and routing guidelines, see the UltraScale Architecture PCB Design User Guide (UG583).