No Input/Output Delays and Partial Input/Output Delays - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English
All I/O ports must be properly constrained.
Recommended: Start by validating baselining constraints and then complete the constraints with the I/O timing.