Power Distribution System - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

Board designers are faced with a unique task when designing a power distribution system (PDS) for a Xilinx® device. Most other large, dense integrated circuits (such as large microprocessors) come with very specific bypass capacitor requirements. Because these devices are designed only to implement specific tasks in their hardened silicon architecture, their power supply demands are fixed and fluctuate typically within a certain range.

Xilinx devices do not share this property. Devices can implement an almost infinite number of applications at user-determined frequencies, and in multiple clock domains.

For this reason, it is critical that you understand the power requirements of the design, which you can assess by completing a power estimation using the Xilinx Power Estimator (XPE). Also refer to the PCB Design Guide for your device to fully understand the PDS placement and generic decoupling requirements prior to a power estimation.

Key factors to consider during PDS design include:

  • Selecting the right voltage regulators to meet the noise and current requirements based on power estimation.
    Note: To enable and simplify your power design, Xilinx partners with key power vendors to design, build, document, and test reference designs that meet all power requirements. For information, see the Power Delivery Solutions tab on the Power page of the Xilinx website.
  • Consolidating power. For supported consolidation options in UltraScale™ devices, see this link in the UltraScale Architecture PCB Design User Guide (UG583).
    Power Tip: Xilinx recommends adding a shunt resistor to allow the power on each rail to be monitored. Alternatively, you can use a PMBus-enabled regulator or current monitoring integrated circuit (IC).
  • Setting up the XADC power supply (Vrefp and Vrefn pins).
  • Running power distribution network (PDN) simulation.

    For UltraScale devices, use the recommended number of decoupling capacitors listed in the UltraScale Architecture PCB Design User Guide (UG583), which are based on the assumptions listed in the guide. If the assumptions differ for your design, simulate your design to determine whether more or less decoupling is required. Running PDN simulations can help to confirm the exact amount of decoupling capacitors required to guarantee power supplies that are within the recommended operating range.

    Note: See the 7 Series FPGAs PCB Design Guide (UG483), UltraScale Architecture PCB Design User Guide (UG583), or Zynq-7000 SoC PCB Design Guide (UG933) to find the details for your device.

For more information on PDN simulation, see Simulating FPGA Power Integrity Using S-Parameter Models (WP411).

Power Tip: Xilinx recommends simulating your power supply design using the SIMPLIS simulator in SIMetrix/SIMPLIS to ensure your design is within the Xilinx recommended operating conditions. The majority of power vendors provide a limited version of SIMPLIS and supply the models to allow you to run this simulation. SIMPLIS is a third-party software used for transient and AC analysis of voltage regulators.
Power Tip: The Vivado tools report_power command can analyze power on a per regulator or voltage regulator module (VRM) basis to ensure the required current on each rail does not exceed the intended power delivery system.