Reduce QoR Variability for Low Reuse Mode - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

In low reuse mode, you can reuse particular cells (for example, a hierarchical cell in the design) or cell types (for example, DSPs or block RAMs). This can be effective when both of the following are true:

  • Some design runs are showing that a design can meet timing but many runs do not.
  • It is early in the design flow or significant changes are still being made.

Reusing hierarchical cells is effective when placement of a particular cell is influencing the WNS significantly. Reusing DSPs, block RAMs, or both is useful in designs that have a relatively high density of these blocks.

To reuse particular cell or cell types:

  • Analyze the reference runs, including checking failing checkpoints to identify the difference between good and bad runs.
    • Identify runs that have a good WNS and low congestion levels.
    • Use floorplanning to define SLR placement.
  • After determining the area to target, compare a set of runs using low reuse mode against a baseline set of runs using the default flow to evaluate effectiveness.
    • Use different place_design directives to generate multiple results for comparison.
Note: In low reuse mode, incremental implementation directives are ignored, and target WNS is always 0.000 ns.

To reuse only block memory placement, use the following Tcl script:

read_checkpoint -incremental routed.dcp \
-reuse_objects [all_rams] -fix_objects [all_rams]

To reuse only DSP placement, use the following Tcl script:

read_checkpoint -incremental routed.dcp \
-reuse_objects [all_dsps] -fix_objects [all_dsps]

To reuse both Block Memory and DSP placement, use the following Tcl script:

read_checkpoint -incremental routed.dcp \
-reuse_objects [all_rams] -reuse_objects [all_dsps] -fix_objects [current_design]

To reuse hierarchy in a particular hierarchical cell and all hierarchies below the cell, use the following Tcl script:

read_checkpoint -incremental routed.dcp \
-only_reuse [get_cells <cell_name>] -fix_objects [get_cells <cell_name>]
Recommended: When reusing a hierarchical module, Xilinx recommends using out-of-context synthesis or incremental synthesis with a PRESERVE_BOUNDARY constraint to ensure cell matching is 100%.