The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 02/18/2021 Version 2020.2 | |
| Title | Changed title to UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs |
| Synchronous Reset vs. Asynchronous Reset | Updated section. |
| Auto-Pipelining Considerations | Updated section. |
| Specifying Constraints for the Vitis Environment | Added new section. |
| Block Design Synthesis | Added information on global synthesis mode vs. out-of-context synthesis mode. |
| Incremental Synthesis | Added information on converting out-of-context synthesis mode to incremental synthesis. |
| Congestion in the Router Log | Updated INFO example. |
| Reducing Clock Delay in UltraScale and UltraScale+ Devices | Added information on the MAX_PROG_DELAY property and on reviewing the row programmable tap delay settings in the Clock Utilization Report. |
| Allow Register Replication | Added information on MAX_FANOUT_MODE. |
| Addressing Congestion | Added information on running report_qor_suggestions. |
| Reusing Placement Results | Updated code example. |
| Recommended Power Constraints | Added new section. |
| Best Practices for Accurate Power Analysis | Added information on report_power confidence level. |
| Connecting a Net to a Free External Pin Using Post-Route ECO | Added new section. |
| 08/14/2020 Version 2020.1 | |
| Design Creation with RTL | Moved into separate chapter. |
| Apply Attributes at the Module Level | Added link to synthesis attribute propagation rules. |
| Using the CLOCK_DEDICATED_ROUTE Constraint | Updated SAME_CMT_COLUMN example. |
| Design Constraints | Moved into separate chapter. |
| Synthesis Flows | Added new section. |
| Synthesis Optimizations | Added new section. |
| Assessing Post-Synthesis Quality of Results | Added new section. |
| Analyzing and Resolving Timing Violations | Added information on Report QoR Suggestions. |
| Using MMCM Settings to Reduce Clock Uncertainty | Updated recommendations and added equations. |
| Using the Timing Report to Determine the Impact of Power Optimization | Updated Tcl example. |