Timing exceptions are subject to strict precedence and priority rules. The most important rules are as follows:
- The more specific the constraint, the higher the priority. For
set_max_delay -from [get_clocks clkA] -to [get_pins inst0/D] 12 set_max_delay -from [get_clocks clkA] -to [get_clocks clkB] 10
set_max_delayconstraint has a higher priority because the
-tooption uses a pin, which is more specific than a clock.
- The exceptions priority is as follows:
set_clock_groups command is not
considered a timing exception even though it is equivalent to two
set_false_path commands between two clocks. It has
higher precedence than the timing exceptions.
set_disable_timing commands disable timing analysis on
specific portions of the design. They have higher precedence than the timing
For details on XDC precedence and priorities, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).