Tip: The report_qor_suggestions
Tcl command flags this issue.
When configuring an MMCM for frequency synthesis, Xilinx recommends configuring the MMCM to achieve the lowest output
jitter on the clocks. Optimize the MMCM settings to run at the highest possible
voltage-controlled oscillator (VCO) frequency that meets the allowed operating range for
the device. The following equations show the relationship between VCO frequency, M
(multiplier), D (divider), and O (output divider) settings to both the input and output
clock frequencies:
Tip: You can increase the VCO
frequency by increasing M, lowering D, or both and compensating for the change in
frequency by increasing O. Increases in VCO frequency negatively affects the power
dissipation from the MMCM or PLL. You can also
make small increases in the VCO frequency when you switch from multiple MMCM clock
outputs using BUFGs to one MMCM clock output using BUFGCE_DIVs, which allows more
clocks to use the fractional divider. When selecting between MMCM and PLL, MMCMs are
preferred because they are able to operate at a higher VCO frequency, have improved
granularity for selecting M and D values, and have fractional dividers
(CLKOUT0).
Different architectures have different VCO frequency maximums. Therefore,
Xilinx recommends regenerating clocking components to be optimal
for your target architecture.
Xilinx recommends
using the Clocking Wizard to automatically calculate M and D values along with the VCO
frequency to properly configure an MMCM for the target device.
Tip: When using the
Clocking Wizard from the IP catalog, make sure that Jitter Optimization Setting is
set to the Minimize Output Jitter, which provides the higher VCO frequency. In
addition, performing marginal changes to the desired output clock frequency can
allow for an even higher VCO frequency to further reduce clock
uncertainty.
The following MMCM frequency synthesis example uses
an input clock of 62.5 MHz to generate an output clock of approximately 40 MHz. There
are two solutions, but the MMCM_2 with a higher VCO frequency generates less clock
uncertainty due to reduced jitter and phase error.
Table 1. MMCM Frequency Synthesis Example
|
MMCM_1 |
MMCM_2 |
Input clock |
62.5 MHz |
62.5 MHz |
Output clock |
40.0 MHz |
39.991 MHz |
CLKFBOUT_MULT_F(M) |
16 |
22.875 |
DIVCLK_DIVIDE(D) |
1 |
1 |
VCO Frequency |
1000.000 MHz |
1429.688 |
CLKOUT0_DIVIDE_F(O) |
25 |
35.750 |
Jitter (ps) |
167.542 |
128.632 |
Phase Error (ps) |
384.432 |
123.641 |