Using a Generated Clock - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

For an output source synchronous interface, the design generates a copy of the internal clock and forwards it to the board along with the data. This clock is usually used as the reference clock for the output data delay constraints whenever the intent is to control and report on the phase relationship (skew) between the forwarded clock and the data. The forwarded clock can also be used in input and output delay constraints for a system synchronous interface.