Using a Pblock to Restrict Clock Buffer Placement - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

When a clock buffer does not need to be placed in a specific clock region, you can use a Pblock to specify a range of clock regions. For example, use a Pblock when a BUFGCTRL is needed to multiplex two clocks that are located in different areas. You can assign the BUFGTRL to a Pblock that includes the clock regions between the two clock drivers and let the placer identify a valid placement.

Note: Xilinx does not recommend using a Pblock for a single clock region.