- In the Flow Navigator, under Program and Debug, click Generate
This synthesizes, implements, and generates a bitstream for the design.
The No Implementation Results Available dialog box appears.
- Click Yes.
After bitstream generation completes, the Bitstream Generation Completed dialog box appears. Open Implemented Design is selected by default.
- Click OK.
- Inspect the Timing Summary report and make sure that all timing constraints
have been met.
You can use the generated bitstream programming file to download your design into the target FPGA device using the Hardware Manager. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).