In this step, you make minor changes to the RTL design sources. These changes necessitate resynthesizing the netlist and re-implementing the design.
- In the Hierarchy tab of the Sources window, double-click the top-level VHDL
arnd1, to open the file in the Vivado IDE text editor, as shown in the following figure.
- Go to line 65 and make swap the inputs to
xReg. The following code snippet shows the required changes:
begin process (clk) begin if rising_edge(clk) then xStepReg <= xStep; uReg <= u; xReg <= x; end if; end process;
begin process (clk) begin if rising_edge(clk) then xStepReg <= xStep; --uReg <= u; --xReg <= x; uReg <= x; xReg <= u; end if; end process;
- Save the changes by clicking the Save File button in the toolbar of the
As you can see in the following figure, changing the design source files also changes the run status for finished runs from Complete to Out-of-date.