Freeze the boundary of the BDC
This option prevents changes that modify the boundary of a BDC. The boundary includes BDC ports, interfaces, port maps, port widths, and parameters. With this option selected, nothing on the BDC boundary will change. All interfaces will have the port maps preserved, port widths will not change, and no parameters (with the exception of clk_domain property) will propagate from the top-level block design to the BDC and vice versa.
Specify BDC variants for synthesis and/or simulation
User can specify different sources for a Block Design Container. Different sources can be viewed as variants of a BDC. Variants of a BDC can differ in the IP blocks within the same defined boundary of the BDC. Once a variant source block design is added, user can select the active variant among these sources for the top-level BD. This action will update the BDC in real-time to show the contents of the new active variant. In addition, user can specify different sources used for BDC synthesis and simulation.
To access this feature, please contact your Xilinx FAE support team.