To edit the source code of a module, right-click it, and select Go To Source from the context menu, as shown in the following figure.
This opens the module source file for editing, shown in the following figure.
If you modify the source and save it, notice that the Refresh Changed Modules link becomes active in the banner of the block design canvas, as shown in the following figure.
Click Refresh Changed Modules to reread the module from the source file. Depending on the changes made to the module definition, for example, adding a new port to the module, you might see a message such as shown in the following figure.
On the Tcl console, you see the changes that were made to the module, as shown in the following snippet:
WARNING: [IP_Flow 19-4698] Upgrade has added port 'new_port' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'module reference design_1_my_dff8_inst_0_0'. These changes may impact your design. CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'module reference design_1_my_dff8_inst_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.